1. Field of the Invention
The present invention relates to an electrically erasable programmable read-only memory device, or a so-called flash memory device.
2. Description of the Related Art
FIG. 45 is a diagram which schematically illustrates cross-sectional structure of a memory cell in a flash memory, wherein reference numeral 1 denotes a p-type silicon substrate, 2 denotes a drain made up of an n-type diffused layer, 3 denotes a source made up of an n-type diffused layer, 4 denotes a floating gate of polysilicon and reference numeral 5 denotes a control gate of polysilicon.
Data is written into this memory cell by, for example, applying a control gate voltage Vcg=12 [V], a source voltage Vs=0 [V], and applying a write voltage (write pulse) of 6 [V] to the drain 2, so that hot electrons generated near the drain 2 in the p-type silicon substrate 1 are injected into the floating gate 4 as indicated by arrow 6.
In order to read the data, on the other hand, a control gate voltage Vcg=5 [V], a source voltage Vs=0 [V] and a drain voltage Vd=1 [V] are applied, whether a current flows into the drain 2 or not is judged, and thus whether the stored data is "1" or "0" is judged.
In order to erase the data, furthermore, a control gate voltage Vcg=0 [V] is applied, the drain 2 is left open, an erase voltage (erase pulse) of 12 [V] is applied to the source 3, and electrons are drawn from the floating gate 4 into the source 3 as indicated by arrow 7.
Here, the erasing is batchwisely effected for all the memory cells in the selected block or chip, and is carried out in the conventional flash memory according to a procedure as shown in FIG. 46.
First, VPPH=12.0 [V] is applied to a VPP (write/erase voltage) terminal which is one of the external terminals.
Next, an erase setup instruction and an erase instruction are consecutively input, whereby a counted value N of a loop counter is set to N=1. Then, the erase voltage is applied to the source of the memory cell for a period of, for example, 10 ms to effect a first time of erasing and, then, erasing is verified.
When there exist non-erased memory cells as a result of verifying the erasure, the value N is increased to N=N+1 within a range in which the counted value N of the loop counter does not exceed a maximum counted value Ne, e.g., 3000 times, and the application of erase voltage to the source of the memory cell and the verification of erasure are repeated.
When there exist non-erased memory cells as a result of verifying the erasure and when the counted value N of the loop counter comes into agreement with a maximum counted value Ne, an error processing is carried out.
When there no non-erased memory cells exist as a result of verification of erasure, the VPP terminal assumes a voltage of, for example, VPPL=0 to 0.65 [V], and the erase mode is finished.
FIG. 47 shows erase characteristics of a memory cell, wherein the abscissa represents the total time of applying the erase voltage and the ordinate represents the control gate voltage.
In FIG. 47, when the control gate voltage is larger than a value represented by a solid line 9, the memory cell is recognized to be turned on and when the control gate voltage is smaller than a value represented by the solid line 9, the memory cell is recognized to be turned off.
As will be obvious from FIG. 47, the data is not completely erased unless the total time of applying the erase voltage becomes longer than a predetermined period of time. In the conventional flash memory, however, the erasure is necessarily verified after the erase voltage is applied to the source of the memory cell from the start of the erasing operation, i.e., even during a period in which the erasure does not need to be substantially verified. Accordingly, extended periods of time are required before the erasing is finished.